This application claims priority from Korean Patent Application No. 2002-1875, filed on Jan. 12, 2002, the contents of which are herein incorporated by reference in their entirety for all purposes.
This disclosure generally relates to semiconductor memories, and more specifically, to a NAND flash memory having verifying functions for data bits held in page buffers during operation modes of programming, erasing, and copy-back programming.
A NAND flash memory, a kind of nonvolatile memory, employs page buffers for latching data (i.e., page data) assigned to a selected page during a read operation, which is referred to as a xe2x80x9csensing operationxe2x80x9d of the page buffers, while storing data (i.e., program data) supplied from the external during a programming operation, which is referred to as a xe2x80x9cdata loading operationxe2x80x9d of the page buffers. Further, the page buffers contribute to prevent program-inhibited cells or programmed cells from being programmed undesirably. When a verifying operation that is checking whether a memory cell is programmed or erased reaches its target (or desired) threshold voltage level, the page buffers detect data bits of memory cells of a selected page, and latch those voltage values. Then, the page buffers provide their data bits into a pass/fail check circuit to confirm those data bits are pass data bits informing of an successive programming or erasing.
Such page buffers have been disclosed in U.S. Pat. No. 5,790,458 entitled xe2x80x9cSense amplifier for nonvolatile semiconductor memory devicexe2x80x9d, U.S. Pat. No. 5,761,132 entitled xe2x80x9cIntegrated circuit memory devices with latch-free page buffers therein for preventing read failuresxe2x80x9d, and U.S. Pat. No. 5,712,818 entitled xe2x80x9cData loading circuit for partial program of nonvolatile semiconductor memoryxe2x80x9d.
One of the known page buffers is shown in FIG. 1. The page buffer of FIG. 1 is connected to a pair of bitlines BLe and BLo, including a pair of latches LAT1 and LAT2 (main and cache). NMOS transistors M1xcx9cM4 form a bitline selection and biasing circuit, which connects one of the bitlines to a sensing node SO and causes the other bitline to be in a floating state. Between the bitline BLe and a sensing node SO is an NMOS transistor M1 that responds to a control signal BLSHFe. Between the bitline BLo and the sensing node SO is an NMOS transistor M2 that responds to a control signal BLSHFo. An NMOS transistor M3 is connected between the bitline BLe and a control signal line VIRPWR and an NMOS transistor M4 between BLo and VIRPWR. The NMOS transistors M3 and M4 respond to control signals VBLe and VBLo, respectively. The transistors M1xcx9cM4 form a bitline selection and biasing circuit to connect one of the bitlines to the sensing node SO and causes the other bitline be in a floating state.
Between a power supply voltage VCC and the sensing node SO is a PMOS transistor M5 that responds to a control signal PLOAD. A PMOS transistor M6 is connected between VCC and a main latch node nB of the main latch LAT1, controlled by a signal PBRST. Between the latch node nB and a ground voltage VSS are NMOS transistors M7 and M8, in series, responding to a voltage level of the sensing node SO and a control signal PBLHCM, respectively. A PMOS transistor M9 is connected between VCC and an output terminal nWDO, being turned on or off responsively to a logic state of a main latch node B. The output terminal nWDO is led to a pass/fail check circuit shown in FIG. 2. A logic state of the output terminal nWDO is complementary to that of the main latch node B. For instance, the output terminal nWDO is connected to VCC when the main latch node B has a low level. Otherwise, the output terminal nWDO is electrically isolated from VCC, in a floating state, when the main latch node B is set at a high level.
An NMOs transistor M10 connected between the sensing node SO and the main latch node B of the main latch LAT1 responds to the signal BLSLT. Between an internal node ND1 and the main latch node B is an NMOS transistor M11 responding to a signal PBDO. A PMOS transistor M12 is connected between VCC and a cache latch node A of the cache latch LAT2, responding to a signal PBSET. An NMOS transistor M13 is connected between the cache latch node A and the sensing node SO, responding to a signal PDUMP. Between the main latch node A and VSS are NMOS transistors M14 and M15 in series. The NMOS transistors M14 and M15 respond to a logic state of the sensing node SO and a signal PBLCHC respectively. Between the internal node ND1 and a cache latch node nA (a counter node of A) of the cache latch LAT2 is an NMOS transistor M16 and between the internal node ND1 and the cache latch node A is connected to an NMOS transistor M17. The NMOS transistors M16 and M17 respond to data signals DLi and nDLi, complementary to each other, respectively.
When a program data bit is xe2x80x9c1xe2x80x9d (as a binary code) to be loaded in the page buffer circuit of FIG. 1, the data signal DLi is logically set to a high level while the data signal nDLi is established at a low level. The internal node ND1 is connected to a data line DLi through NMOS transistors M18 and M19 those form a column gate circuit responding to column selection signals YA and YB respectively. Between the data line DLi and the ground voltage is an NMOS transistor M20, responding to a signal DLD.
The page buffer shown in FIG. 1 is operable in erasing, programming, reading, and copy-back programming modes. The copy-back programming is referred to an operation of moving data stored in a page into another page, having been proposed in U.S. Pat. No. 5,996,041 entitled xe2x80x9cIntegrated circuit memory devices having page flag cells which indicate the true of non-true state of page data therein and methods of operating the samexe2x80x9d.
In programming with the page buffer of FIG. 1, a program data bit is loaded into the latch LAT2. For instance, if a program data bit is xe2x80x9c1xe2x80x9d, a data signal DLi becomes a high level while a data signal nDLi becomes a low level. The NMOS transistor M16 is turned on while an NMOS transistor M17 is turned off. At the same time, NMOS transistors M18 and M19 are turned on by column selection signals YA and YB, thereby connecting the latch node nA to the data line DLi through M18 and M19. For loading the program data bit, the data line DLi is connected to a ground voltage through the NMOS transistor M20. Thus, the program data bit of xe2x80x9c1xe2x80x9d is loaded into the latch node A. If a program data bit is xe2x80x9c0xe2x80x9d, the data signal DLi becomes a low level while the data signal nDLi becomes a high level. As the NMOS transistor M17 connects the latch node A to the data line DLi that is at the ground voltage, the program data bit xe2x80x9c0xe2x80x9d is loaded into the latch node A. Through the aforementioned procedure, all program data bits are loaded into the page buffers in sequence.
After completing the loading operation of the program data bit into the cache latch LAT2, the data bit is transferred to the main latch LAT1. First, the main latch LAT1 is initiated by a turn-on of an NMOS transistor M6 and the sensing node SO is charged up to a high level by a PMOS transistor M5. And then, an NMOS transistor M13 is turned on to transfer the program data bit from LAT2 to LAT1. If the program data bit of xe2x80x9c1xe2x80x9d has been loaded in the cache latch LAT2, it is latched at a node B of LAT1 when NMOS transistors M7 and M8 are turned on. On the contrary, when the program data bit of xe2x80x9c0xe2x80x9d is loaded in the cache latch LAT2, the NMOS transistor M7 is turned off and thereby the node B of LAT1 maintains its initial state regardless of a turn-on of the NMOS transistor M8 by a control signal PBLCHM.
The program data bit loaded in the main latch LAT1 is put into a program operation for a selected bitline for which a selected memory cell will be programmed, while the other non-selected memory cells will be program-inhibited. During programming with the data bit held in the main latch LAT1, the cache latch LAT2 as a cache brings the next program data bit thereto.
The main latch LAT1 detects data bits stored in memory cells belonging to a selected page during a read operation or a program-verifying operation, while the cache latch LAT2 does so during a copy-back program operation or an erasure-verifying operation.
In the read or program-verifying operation, once the bitlines BLe and BLo and the sensing node SO have been discharged, a selected bitline (e.g., BLe) is placed in a floating state after being charged up to a predetermined voltage. While this occurs, the bitline voltage will be reduced or maintains its prior level. A current is supplied to the node SO through the NMOS transistor M5 while the NMOS transistor M1 is conductive. If the selected memory cell is an on-cell, the current of the node SO flows out through a channel path of the selected memory cell, resulting in lowering the voltage of the node SO below the threshold voltage of the NMOS transistor M7. The latch LAT1 does not vary its voltage state although the NMOS transistor M8 is turned on. If the selected memory cell is an off-cell, the current from the NMOS transistor M5 contributes to increase the voltage at the node SO gradually up to a higher level over the threshold voltage of the NMOS transistor M7. During the time NMOS transistor M8 is conductive, the latch node B is connected to the ground voltage to reverse or maintain the logical state of the main latch LAT1.
In a copy-back program or an erasure-verifying operation, the cache latch LAT2 detects data bits stored in memory cells of a selected page and then transfers the sensed result to the main latch LAT1. In detail, the bitlines BLe and BLo and the sensing node SO are discharged and the selected bitline (e.g., BLe) is caused to float after being charged up to a predetermined voltage. With a turn-on of the NMOS transistor M1, a current is supplied to the node SO through the PMOS transistor M5. If a selected memory cell is an on-cell, the current supplied to the node SO flows out through the selected memory cell, resulting in the voltage at the node SO under the threshold voltage of the selected memory cell. The main latch LAT1 maintains the current state although the NMOS transistor M15 may turn on by a transition of the control signal PBLCHC from a low level to a high level. If the selected memory cell is an off-cell, the current from the PMOS transistor M5 charges the sensing node SO gradually, resulting in an increase of the voltage of the node SO over the threshold voltage of the NMOS transistor M14. The NMOS transistor M15 is turned on to reverse a logic state of the cache latch LAT2. Thereby, the cache latch LAT2 detects a state of the selected memory cell, which is transferred to the main latch LAT1.
Programming or erasing accompanies a verifying operation to confirm whether a memory cell programmed or erased is settled at a predetermined threshold voltage. The result of programming or erasing a memory cell of a selected page is decided by a logic state held in the main latch LAT1, together with a pass/fail check circuit shown in FIG. 2. The pass/fail check circuit 2 of FIG. 2, which is a wired-OR type, generally includes multiple fuses F1xcx9cFk, an NMOS transistor M21, an inverter INV5, and a latch LAT3. The fuses are connected to output terminals nWDO of page buffers 3, each to a group of the page buffers. Each fuse is blown when there is at least a defect in its corresponding bitlines.
The output terminal nWDO assigned to each page buffer is set by the latch node A of the main latch LAT1 (FIG. 1). For instance, if the latch node A is set at a high level, the PMOS transistor M9 is turned on to make the output terminal nWDO a high level, informing that the selected memory cell is completely programmed or erased. In this case, a node ND2 maintains a low level to make a pass/fail signal PF a low level. If the latch node A is at a low level, the PMOS transistor M9 is turned off, informing that the selected memory cell is not yet fully programmed or erased yet. In this case, the high level of the node ND2 makes the pass/fail signal PF a high level.
Because one fuse is assigned to a group of page buffers or bitlines (because it is impossible to associate them to each single page buffer with the present design techniques), it is inevitable to abandon plural page buffers connected to the blown-out fuse when one of bitlines corresponding thereto has a defect. Such a condition for the fusing architecture needs a more topological dimension, reducing layout efficiencies, as well as increasing a size of a redundant cell array.
Another technique for verifying the results of programming or erasing, free from the disadvantages with the fuses, is xe2x80x9ccolumn scanningxe2x80x9d, which has been proposed in Korean Patent Laid-open No. 2001-029546 entitled xe2x80x9cFlash memory device with a program state detecting circuit and program method thereofxe2x80x9d. In the manner of the column scanning, page buffers store states of memory cells of a selected page after the memory cell states are detected, and then the data bits held in the page buffers are sequentially transferred to a pass/fail check circuit through a column pass circuit (e.g., NMOS transistors M19 and M20 of FIG. 1) by the unit of byte or word in response to an increment of column addresses. During this, a data bit from a page buffer corresponding to a defective column is not accessible because the defective column is substituted with a redundant column by a column address containing its defect information.
However, the column scanning may not be operationally available with the kind of the page buffer 10 shown in FIG. 1 because the cache latch LAT2 is connected to a program data bit of another page during a program operation by the main latch LAT1. As stated above, the cache latch LAT2 is conductive together with the data line DLi in loading a program data bit, which may cause a data conflict between a loading data bit and verifying data bit.
Embodiments of the invention provide a flash memory enhancing efficiencies of verifying operations for programmed or erased memory cells without fuses.
Thus, embodiments can provide a flash memory capable of performing operations of programming, erasing, and copy-back programming, with loading pass data in page buffers corresponding to defective columns.
Additionally, embodiments of the invention provide enhancement efficiencies to a flash memory for verifying operations for programmed or erased memory cells by loading pass data in page buffers corresponding to defective columns.